The invention relates to a semiconductor device test system, a semiconductor device test method, and an interface device for use with such a test method.
Semiconductor devices, e.g. corresponding, integrated (analog or digital) computing circuits, e.g. corresponding micro processors or micro controllers, and/or semiconductor memory devices such as functional memory devices (PLAs, PALs, etc.) and table memory devices (e.g. ROMs or RAMs, in particular SRAMs and DRAMs), etc. are subject to comprehensive tests during and after their manufacturing.
Thus, it is possible to identify and sort out (or repair) defective semiconductor devices or modules; alternatively or additionally—in correspondence with the test results achieved—the layout of the semiconductor devices can be modified, and/or the process parameters used during the manufacturing of the devices may be correspondingly modified or adjusted optimally, respectively, and/or the software program stored on the semiconductor device may be modified.
For carrying out—correspondingly standardized—test methods, a JTAG test module (JTAG=Joint Test Action Group) defined in IEEE standard 1149 may be used.
In accordance with the above-mentioned standard, a JTAG test module—provided on a corresponding semiconductor device—includes a test access port (TAP) that is connected with four or—optionally—five test pins by means of which a test clock signal TCK (TCK=Test Clock), a test mode select signal TMS (TMS=Test Mode Select), a data input signal TDI (TDI=Test Data In), a data output signal TDO (TDO=Test Data Out), and—optionally—a test reset signal TRST (TRST=Test Reset) can be input into/output from the device to be tested.
Semiconductor devices that include corresponding JTAG test modules may—pursuant to the original JTAG standard—, after their incorporation in an electronic system, in particular after soldering with a corresponding printed circuit board, be tested for whether there exists a sufficiently good electrical contact between the semiconductor device pins and the pins of the printed circuit board.
In accordance with recent revisions of the JTAG standard, e.g. corresponding semiconductor device function tests that concern the actual function of the semiconductor device may be performed by a JTAG test module in addition thereto, e.g. corresponding JTAG built-in self tests, and/or a corresponding programming of the device may be performed by means of the JTAG test module, and/or a downloading of memory contents.
Furthermore, a plurality of proprietary, manufacturer-specific, non-standardized test methods are known in prior art, which are in particular used e.g. for testing the devices prior to their incorporation in an electronic system, for instance, for testing semiconductor devices that are still positioned on a corresponding wafer, for testing the semiconductor devices that are available individually after the sawing apart (or the scratching, and breaking) of the wafer, and/or for testing the semiconductor devices incorporated in a corresponding device package.
In so doing, one has been trying to keep the number of pads or pins that are necessary for such tests relatively small.
In the case of so-called SSCM tests (SSCM=“Single Scan Chain Mode”), for instance, by means of only few, e.g. two additional pins, a scan test of the elements provided on a semiconductor device, in particular of memory elements, e.g. flip-flops, can be carried out. Here, e.g. a first additional pin serves for the input of test data, and a further additional pin for the output of test data (wherein the data to be output may, for instance, be stored in a corresponding shift register).
Such proprietary, manufacturer-specific tests can no longer, or only with relatively great effort, be carried out after the incorporation of the corresponding semiconductor device in an electronic system, in particular after the soldering of the semiconductor device with a corresponding printed circuit board—along with further semiconductor devices of different manufacturers.